Digital test systems for checking the performance of integrated circuit devices typically are connected to the input/output pins of the integrated circuit device under test, to apply signals to and/or receive signals from these pins during a pre-established test cycle. The information which is obtained from the test circuit, through the performance of the device under test, and from the signals received from it, is employed to determine the proper functioning or malfunctioning of the device under test, as evidenced by the behavior of the device during the test cycle.
In many integrated circuit devices, CMOS technology is employed, and CMOS gates, which are connected to the bi-directional input/output pins, are capable of having one of a possible three different states or modes of operation. The pin connected to the gate may be configured to receive either a valid input high (VIH) or a valid input low (VIL) from the test system, when the pin is functioning in an input state, and a second "open-circuit" state, which is known as a "tri-state" or a "floating" state of operation. Similarly, in the third state when the pin is supplied with output signals from the gate, the output signals can be a valid output high (VOH) or valid output low (VOL).
In some test situations, when the switching times for the bi-directional input/output pins are being characterized by a test circuit, a problem has been encountered during the "tri-state" or "floating" portions of the tester cycle. For example, for some applications the bi-directional input/output pins are required to switch from a test device input state to a floating or tri-state mode, to a device output state, and finally, back to a tri-state or floating condition. When such cycling of input signals and output signals from the device under test are separated by tri-state modes of operation, the signals on the input/output pins whenever they are switched from a valid input/output level to the tri-state mode, begin to decay.
The result of the decay is capable, in at least some applications, of eventually tripping the threshold for a valid input signal, even though no such signal was supplied to the device from the tester circuit. For systems where the input/output pins are active at a level to which the signal decays, such a decay causes incorrect memory read and memory write functions during refresh cycles of memory devices included on such devices. Other incorrect operating functions also can occur, thereby invalidating the test results.
It is desirable to prevent a drift or decay of the signal level on the input/output pins of an integrated circuit device under test, during the tri-state or floating condition of operation of the integrated circuit devices connected to an input/output pin, whenever the pin of the device under test is being sequenced through an appropriate input and output test cycle.